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  • 1TeraFLOP (FP64) on Intel phi coprocessor unit : MIR PRO speed up up up ... ?

    http://www.intel.com/content/www/us/en/high-performance-computing/high-performance-xeon-phi-coprocessor-brief.html

    Intel has finally unveiled Xeon Phi (codenamed Knights Corner), a range of more-than-50-core 22nm coprocessors built with the new Many Integrated Core (MIC) architecture. Xeon Phi is the end result of a project that began with the Larrabee architecture in 2006. Larrabee was initially meant to be a GCGPU, much like Nvidia’s Fermi and Kepler cores, but based on the x86 instruction set.

    The graphics guts were stripped out, and all that remained were 50+ Pentium 1 (P54C) cores, with the addition of some juicy floating-point and vector processors. Intel has confirmed that each MIC core, like Larrabee, has a monstrous 16-wide ALU capable of 512-bit SIMD. These Xeon Phi coprocessors (which come in a PCIe add-in card form factor) will be available in a few flavors, probably starting at 50 cores and with 8-16GB of GDDR5 RAM. Intel is targeting real-world performance of 1 teraflops per coprocessor, which is well above the Tesla M2090 (a Fermi-based card) and AMD’s HD 7970. The key difference, though, is that Xeon Phi uses the mature and very-well-understood x86 architecture, and is supported by Intel’s best-in-class compiler toolchain. Nvidia’s Kepler-based Tesla cards might be faster than 1 teraflops — but that’s theoretical performance. The fact of the matter is that writing and compiling software to effectively use hundreds of CUDA cores is incredibly hard.

    And therein lies the crux: Xeon Phi might not have the edge on raw performance, but it’s infinitely easier to deploy. The vast majority of current HPC installations use Intel or AMD x86 chips and software.

    http://goparallel.sourceforge.net/scien ... -xeon-phi/
    ...
    The scientists main result is that Intel’s Xeon Phi offers unique opportunities for parallel processing by allowing programmers to choose from among three primary methods of partitioning their parallel code for maximum speed and minimum execution times–native, off-load and heterogeneous–compared to general purpose graphic processing units (GPGPUs) which only operate in offload mode.

    Their comparisons of native, offload and heterogeneous modes is based on extensive testing regimes derived from NICS deep-and-wide experience in petaFLOP-caliber <A HREF=”http://intel.ly/m0NW2O”>parallel processing</A> and AACE’s mission of developing multi-processing methodologies, distributing the knowledge gained throughout the HPC community, and providing expert feedback to supercomputer vendors to guide the development of future architectures and programming models.

    “The Intel Xeon Phi differentiates itself from GPGPUs by using x86-compatible cores, which allow the coprocessor to support the same programming models and tools as the Intel Xeon processor,” said Betro. “This allows scientific application programmers to accelerate highly parallel programs with little to no code modification, thus allowing them to focus on simply tuning the algorithms for performance.”
    ...


  • And by the time this filters down to the (Everyman), the year will be???


  • 2112 D.C.


  • Intel's Xeon Phi processor family gets ready to debut later this year (=2012). It is a unique solution currently: x86 FPU coprocessor.

    The real problem is that the application must support the coprocessor with the "small" code adjustments (=VSL support).

    The real news is that Xeon phi it’s infinitely easier to deploy...